Serializer/deserializer (SerDes) receivers facilitate the transmission of parallel data through a serial link by converting parallel data to serial data, transmitting the serial data through a communications channel, then converting the serial data to parallel data. Signal distortion, loss, noise, or other dispersion effects introduced by the communications channel may require signal equalization in order to correct for inter-symbol interference (ISI) or other impairments. In a digital SerDes receiver, an analog to digital converter (ADC) for sampling and digitizing the received analog signal may be implemented as an analog/mixed signal circuit and all processing of the digitized signal may be accomplished in a digital domain data path. The digital data path may include a variety of filters and equalizers, e.g., a feed forward equalizer (FFE) or a decision feedback equalizer (DFE).
If the data path includes a decision feedback equalizer there will be a “cursor” or received bit currently being processed by the DFE. Similarly, “post-cursor” bits are consecutive bits already processed by the DFE and “pre-cursor” bits are not yet processed by the DFE. The decision feedback equalizer can only correct ISI caused by post-cursor bits; however, inter-symbol interference can also be caused by pre-cursor bits. For optimal SerDes receiver performance, a feed forward equalizer is often used to correct ISI generated by pre-cursor bits. A combination of a feed forward equalizer and decision feedback equalizer, therefore, can correct both pre-cursor and post-cursor ISI. A data path featuring a feed forward equalizer of fixed size followed by a decision feedback equalizer may be used to provide ISI correction via a fixed number of pre-cursor and post-cursor taps.